This invention relates generally to input signals (e.g., clock signals) in integrated circuits, and, more particularly, relates to multiplying and/or reshaping such input signals.
In many digital systems, such as those including microprocessors and digital signal processors, the incoming clock needs to be reshaped and/or multiplied. Multiplication is typically accomplished using a phase lock loop (PLL) circuit. PLL circuits lock a generated signal to a reference signal using a feedback control system that brings the two signals into a fixed phase relation. Traditional PLL circuits contain analog components, such as voltage controlled oscillators (VCOs). Manufacturing integrated circuits with analog components results in non-uniform and error-prone products. For example, a design produced by multiple foundries can have different electrical characteristics because of slight variations in the fabrication process. Additionally, analog components must be calibrated, which adds cost and may introduce error.
To overcome the problems of analog components, digital PLL circuits were developed. Known digital PLL circuits require a high frequency input reference signal that allows small clock phase adjustments to be made to a generated output signal. Typically, phase correction is accomplished by a feedback loop wherein the output signal is fed back into a phase comparator for comparison with the input clock. To use such digital PLL circuits, the high frequency input reference signal is typically a much higher frequency than the generated output signal. For example, the reference signal may be twice the frequency of the output signal.
The generated output signal may be used to drive a microprocessor or other integrated circuits. However, recent microprocessors require high frequency clocks. For example, with existing technology, the PLL circuit needs to generate an output signal of nearly 500 MHz. And within a relatively short period of time, for example 3 years or so, microprocessors are expected to run with a 1 GHz clock signal. In order for current PLL circuits to generate a 500 MHz clock, a 1 GHz input reference signal is needed. However, such high-frequency clocks are expensive and difficult to manufacture. Consequently, as microprocessor speeds increase, generating an input reference signal running at a sufficient frequency is becoming increasing problematic.
The output signal may also need to be reshaped. Reshaping may be necessary to obtain a clock signal with a 50/50 duty cyclexe2x80x94a clock signal that has symmetrical high and low states. A 50/50 duty cycle may be obtained by dividing an input clock in half, since the period of the clock signal is assumed constant. However, as already described, dividing a clock signal in half before feeding it to a microprocessor has significant drawbacks, since there are practical limitations on the frequency of the source clock.
Another option for reshaping a clock signal is shown in Bxc3xa9chade, U.S. Pat. No. 5,179,294. The reshaping circuit of Bxc3xa9chade and other digital PLL circuits use delay elements to determine a period of the incoming clock signal. The delay elements are subject to voltage and temperature fluctuations, which can vary the length of the delay. Such variations in the delay elements cause an inconsistent duty cycle in the generated output signal, which effects the performance of the overall circuit.
In one embodiment, a multiplier circuit is disclosed that multiplies and/or reshapes an input signal. The multiplier circuit in this embodiment is primarily digital so that an integrated circuit produced by one foundry will have similar electrical characteristics as the same circuit produced by another foundry. Additionally, the multiplier circuit does not require a high frequency reference clock, making it more practical and economical as microprocessor speeds increase.
In one aspect of the illustrated embodiment, a period determining circuit is used to determine the period of an input signal and to convert the period to a digital number, such as a binary number. The period determining circuit may include a delay circuit, a comparator, and an edge detector to continuously or repetitively determine the period of the input signal. A count leading edge may then be used to convert the period into a binary number.
In another aspect of the illustrated embodiment, an adder may be used in conjunction with a multiplier/divider to calculate the average of the period over a predetermined number of cycles. Thus, by calculating an average period, imperfections in the delay circuit due to voltage fluctuations are in effect cancelled.
In yet another aspect of the illustrated embodiment, a variable multiplication control is applied to the multiplier/divider to multiply the averaged signal. The multiplier/divider may be a shifter circuit and the multiplication control may in this case control the direction and the number of bits that are shifted. The shifter may take into account both the division needed for calculating the average period and the multiplication simultaneously. The shifter may be set to shift the accumulated number calculated by the adder.
In yet a further aspect of the illustrated embodiment, a variable delay line is coupled to the multiplier/divider to generate the multiplied or reshaped output signal. A multiplexer may be used to synchronize the variable delay and the original input signal so that phase matching is constantly monitored and maintained.
These advantages and other advantages and features of the inventions will become apparent from the following detailed description, which proceeds with reference to the following drawings. The present invention relates to the novel and non-obvious aspects of the invention individually as well as collectively.